The present invention relates to a method for controlling microprocessors which enables a high speed transfer of data between microprocessors.
FIG. 3 is a block diagram showing a conventional processing system for transferring data between two microprocessors.
As shown, between a first microprocessor 1 and a second microprocessor 2, five lines and the data bus are shown respectively for transferring a select signal 3 for the microprocessor 2 (referred to as an MP2 select signal), a select signal 4 for the microprocessor 1 (referred to as an MP1 select signal), a busy signal 5 for the microprocessor 1 (referred to as an MP1 busy signal), a busy signal 6 for the microprocessor 2 (referred to as an MP2 busy signal), a clock signal 7, and data 8.
The number of the data lines contained in the data bus corresponds to the number of processing bits of the microprocessors. The additional lines respectively for the other signals and the clock signal, and a ground line (not shown) used in common to each line are provided between the microprocessors 1 and 2.
Next, the operation of the arrangement shown in FIG. 3 will be described with reference to FIG. 4.
In order to transfer data from the microprocessor 1 to the microprocessor 2, for example, at first, the microprocessor 1 checks the MP2 busy signal 6 sent from the microprocessor 2 and determines whether or not the microprocessor 2 is in a data-receivable state.
When the processor 1 determines that the MP2 busy signal 6 indicates a non-busy state of the microprocessor 2, the microprocessor 1 sends out the MP2 select signal 3 to the microprocessor 2. The microprocessor 2 enters into a data-receivable state in response to the MP2 select signal 3.
On the other hand, the microprocessor 1 outputs data 8 in synchronism with the clock signal 7. The microprocessor 2 receives the data 8 in synchronism with the clock signal 7 (the leading edge of the clock signal).
In the converse case, that is, in the case of transferring data from the microprocessor 2 to the microprocessor 1, like operations are carried out by using the MP1 select signal 4 and the MP1 busy signal 5 in place of the MP2 select signal 3 and the MP2 busy signal 6.
The foregoing arrangement, however, needs to synchronize the microprocessors, resulting in taking a certain length of time to send and receive data. Hence, the arrangement is limited with respect to achieving a higher speed operation for sending and receiving data between the microprocessors.